Chemical-mechanical planarization (“CMP”) processes are frequently used to planarize the surface layers of a wafer or other substrate in the production of ultra-high density integrated circuits. In typical CMP processes, a wafer is pressed against a slurry on a polishing pad under controlled conditions. Slurry solutions generally contain small, abrasive particles that mechanically remove the surface layer of the wafer. Slurry solutions may further contain chemicals that assist the removal process. The polishing pad is generally a planar pad made from a relatively soft, porous material, such as blown polyurethane. The wafer is abraded by the abrasive particles, thereby leveling or planarizing the surface of the wafer. After the wafer is planarized, it is cleaned to remove residual particles on the surface of the wafer that were introduced to the CMP process by the slurry, the polishing pad or the wafer itself. As an alternative to slurry solutions, the abrasive particles may be carried by the pad itself.
CMP processing is particularly useful for planarizing a metallic surface layer used to form conductive features, such as interlayer connectors and/or conducting lines. As an example, these interconnects are often formed by a method known as a dual damascene technique. Using the dual damascene technique, contact vias and conductor trenches are patterned into an insulating layer of a semiconductor wafer and a layer of metal is formed over this structure. This blanket layer of metal fills the vias and trenches and covers the upper surface of the wafer. Excess metal formed on the upper surface of the wafer is then removed by CMP to a level at or below the surface of the insulating layer.
After the excess metal is removed, residual materials from the slurry, polishing pad or wafer remain on the planarized surface of the wafer. The residual materials commonly include particles attracted to the surface of the wafer, such as by electrostatic or mechanical forces, as well as material bonded to the surface of the wafer. Residual materials attracted to the surface of the wafer may include abrasive particles from the slurry and particles of the metal layer removed from the surface of the wafer. Residual materials bonded to the surface of the wafer may include any remaining excess metal not removed during the planarization. To reduce defects in the finished integrated circuit device, it is generally necessary to clean such residual materials from the planarized surface of the wafer prior to further processing.
A common post-CMP cleaning approach is to use a slurry dispersant to first remove the materials attracted to the surface of the wafer. Slurry dispersants may include deionized (DI) water to simply flush such residuals from the surface of the wafer. Mechanical action, such as brush scrubbing or megasonics, may assist the removal of these attracted residuals. The slurry dispersant may also include materials to complex or otherwise bind such residuals to aid in their removal.
After removal of the materials attracted to the surface of the wafer, the wafer is often etched to remove the material bonded to the surface of the wafer. Such residuals generally are unaffected by slurry dispersants. As these residuals are typically remaining patches of the conductor material, their removal is also important to proper device performance.
In these two-step approaches, the appropriate slurry dispersants and etchants are highly dependent upon their respective target residual materials. Often, the slurry dispersants and etchants may be incompatible with each other, thus requiring a cleaning step to remove traces of the slurry dispersant before etching the bonded residuals. Each processing step creates added cost and the opportunity for introducing additional defects into the integrated circuit device.
In the competitive semiconductor industry, it is desirable to maximize the yield of finished wafers. The uniformity of the planarized surface and maximization of yield is, in part, a function of the effectiveness and repeatability of the solutions and processes used for the removal of residuals following CMP. While a wide variety of dispersant and etchant solutions are available, these solutions are generally specific to the composition of the material to be removed. One must also avoid damaging the surrounding materials.
As device sizes continue to decrease, designers must turn to higher-conductivity materials for use in interconnect lines and contacts to replace aluminum and its alloys. Some of these higher-conductivity materials include silver and its alloys.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative solutions and methods for removing planarization residuals in the fabrication of integrated circuit devices, particularly following mechanical removal of a silver-containing layer.